Multi-Stage Jitter Reduction
Jitter is an undesirable artifact that is unique to digital audio. In the digital domain, music is represented by a discrete series of samples spaced at a regular time interval. To convert these discrete samples into the analog domain, they must be recreated at regular, precisely-spaced time intervals. This is where the timing error, called "jitter," seeps in. The distortion caused by jitter is non-harmonically related to the signal and sounds unnatural, fatiguing, and harsh. Our goal is to diminish this timing error to a level where it can no longer be perceived.
Various solutions exist for reducing jitter. Some of them work quite well in taming the amount of jitter, but in the process, they may generate other digital artifacts that are undesirable and ultimately degrade sonic quality.
In designing a jitter-reduction circuit, we have two main goals in mind. The first goal is to preserve the original samples in their bit-perfect condition as far as it is possible so that the jitter-reduction process does not introduce digital artifacts. The second goal is to make it work consistently over a wide range of digital interfaces -- USB, SPDIF, and Toslink -- so that the listener may enjoy natural sound regardless of the source of music. In order to achieve such goals, we have devised a multi-stage jitter-reduction strategy that progressively lowers jitter until it becomes insignificant.
Jitter Reduction Stage 1
At the first stage of jitter reduction are high-performance digital transformers for rejecting high-frequency common-mode noise from digital sources. These transformers, made by Scientific Conversion, are optimized specifically for ultra low primary to secondary capacitance (0.5 pF), the most critical parameter for common-mode rejection. Thus, the jitter due to the common-mode noise is eliminated right at the input, even before it reaches the digital receiver circuit.
In addition, the digital transformers completely isolate the noisy grounds of a computer, CD, DVD, Blu-ray player, or music server, cutting off the ground loops and keeping the DAC ground clean.
Jitter Reduction Stage 2
The remaining jitter from the incoming digital data is reduced further through the 2nd stage, implemented using the Wolfson WM8805 digital interface receiver. Often at this stage, a sample-rate converter is used to reduce jitter. However, a conventional sample-rate converter modifies every sample based on a constantly-changing estimate of the input sample rate, inevitably introducing audible artifacts. By contrast, the WM8805 relies on an elastic buffer that absorbs timing errors without modifying the original samples in any way.
In a nutshell, the incoming samples, with their jittery clock, are temporarily stored in the elastic buffer. As they fill up the elastic buffer, they are sequentially read out, controlled by a precision clock from a crystal oscillator. The rate of readout is determined by a PLL (Phase-Locked Loop), which tracks the difference between the incoming clock frequency and the reference clock frequency and makes an adjustment to ensure that the elastic buffer does not overflow.
The chief advantage of this approach is that the audio samples remain bit-perfect, completely unmodified. The only change is the timing information, now referenced to a clean crystal oscillator. The WM8805 can tolerate a very wide range of incoming jitter, and almost all it is absorbed by the elastic buffer, leaving only a small amount of residue (50 ps rms) to the last stage.
Jitter Reduction Stage 3
The final refinement is performed by the ES9018 DAC, with its unique sample-rate conversion technology (patented by ESS Technology, US patent 7330138). It transports the original samples to a completely new clock domain, run by an ultra low phase noise oscillator. The new clock domain is at a much higher frequency (80 MHz in the case of the D1 DAC). Initially, the audio data is oversampled to the new domain simply by duplicating the samples, as indicated by the repeated dots in the diagram. Because the two sample frequencies are unrelated, the sample times of the two clocks will not align exactly. Note that almost all the samples of the output are simple replicas of the input. Only at the point where the input sample changes does the timing mismatch become an issue.
As shown in the figure zoomed into a transition point, the output sample clock falls slightly after the input sample clock, which causes a portion of the signal to be missing (the shaded area). It is this missing area that must be corrected. The key to ESS Technology's innovation lies in transforming this sampling-time mismatch into a single intermediate sample that corrects for the timing error. At the transition point, it generates a new intermediate sample in such a way to match the shaded area caused by the timing mismatch. Thus, the time error is transformed into an equivalent digital level.
To calculate the shaded area, the position of the input clock relative to the reference clock must be determined accurately. This critical task is performed by a DPLL (Digital Phase-Locked Loop), which locks onto the input clock and compares it to the precision low phase noise reference. The whole process is extremely accurate, achieving errors less than -175 dB.
In summary, Anedio's multi-stage jitter reduction circuit accomplishes the two main goals mentioned at the beginning. It keeps the bit-perfect condition until the last stage, where it performs the fine-level jitter correction with extreme accuracy. This assures that whatever the listener hears is as close to the original as it can get. In addition, the wide range of jitter correction can effectively deal with for all types of digital inputs -- USB, SPDIF, and Toslink, enabling the listener to enjoy consistently natural sound regardless of the music source.